Architecture Support for the Algorithms
In the past, the high-speed math that is required to implement the above described algorithms quickly enough to generate smooth, complex motion profiles has often required a special processor, typically a digital signal processor (DSP).
Algorithms such as those described above that perform repetitive operations on large amounts of data are particularly well-suited to the application of DSPs (Figure 1, below). There are drawbacks to using DSPs for motion control, however, including hardware cost and system/software complexity.
 |
| Figure 1. Many legacy industrial systems are built from multiple processing platforms, each with its own processor architecture, sometimes including expensive, hard-to-program DSPs |
A DSP is poorly suited to general purpose computing tasks. Since DSPs are generally not supported by general purpose operating system (GPOS) functions, they typically cannot support a user interface or easy access to file and network I/O, without expensive custom programming and interfacing.
A DSP's instruction repertoire is focused on providing functions designed to quickly execute basic mathematical functions on multiple operands. DSP instruction sets typically include a set of very fast multiply-and-accumulate (MAC) instructions or Single Instruction Multiple Data (SIMD) instructions that perform matrix math evaluations for algorithms that are used frequently in machine vision and complex motion control applications.
Because DSPs don't do general purpose computing well, typically they are used as imaging or motion control co-processors connected to general purpose processors in hybrid-architecture systems.
A more cost effective way of building systems, enabled by the advent of multi-core general purpose processors that incorporate SIMD instructions with DSP-like functionality in their instruction sets, is to build industrial control systems using a single architecture.
The SIMD instructions that comprise much of the code in DSP applications have an analog in many modern general-purpose processors; in Intel' Architecture Processors these instructions are also known as the Intel Streaming SIMD Extensions (Intel SSE) instructions.
Like a DSP, these instructions perform mathematical operations very efficiently on large arrays of data. Unlike with a DSP in a co-processor arrangement, a general-purpose processor that supports SIMD is capable of integrating general application algorithms with the complex mathematical algorithms as part of a unified logical execution stream in a single processor.
