Monterey, Calif. -- Power issues charged up the FPGA 2006 symposium here last week, and for good reason--many observers see high power consumption as perhaps the biggest factor limiting wider usage of the devices.

It's technically feasible to build an FPGA for mobile, battery-powered applications, said a Xilinx Inc. researcher at this research-oriented conference. But finding the right balance between power reduction and the trade-offs it brings is challenging, participants said. At an evening panel discussion titled "Will power kill FPGAs?" no one disagreed that ASICs still hold an overwhelming power advantage over FPGAs.

The Xilinx paper, presented by researcher Tim Tuan, described a research project in which Xilinx built a low-power architecture based on the company's Spartan 3 fabric. Applying such optimizations as voltage scaling, power gating, low-leakage configuration memory and sleep mode, the resulting Pika architecture is said to produce 46 percent less active power and 99 percent less standby power than the baseline Spartan 3--at the expense of a 27 percent performance loss and 40 percent area penalty.

"Power consumption is clearly the No. 1 factor holding up FPGAs from penetrating the vast majority of consumer applications," noted Bryan Lewis, analyst at Gartner Dataquest. "If these [Xilinx] low-power claims can be met in volume production, this could provide a significant upside to the future FPGA market."

But are the performance and area trade-offs worth it? If not, the conference revealed more modest approaches, such as a technique currently used in Altera Corp.'s Quartus tool for power-aware mapping of embedded RAM blocks. As described by researchers from Altera and the University of Massachusetts, that approach reduces memory dynamic power by 21 percent and overall dynamic power by 7 percent, at just a 1 percent cost in performance and logic.

Designers have long known that FPGAs have far worse power consumption than ASICs, but quantification has been lacking. A paper presented by Ian Kuon, PhD student at the University of Toronto, showed just how large the gap can be. The authors used a broad series of RTL benchmarks to compare a 90-nanometer Altera Stratix II implementation to a 90-nm CMOS standard-cell ASIC implementation from STMicroelectronics. Tool flows included syn- thesis, placement and routing. The benchmarks were derived from open-source designs at www.opencores.org and from University of Toronto research projects.

Dynamic power, the re- searchers found, was on average 12 times worse for the Stratix FPGA over the range of benchmarks. It didn't much matter whether simulation or a toggle test was used to compute the results. The gap narrowed slightly with hard blocks on the FPGA.

Static power presented a more complex picture. Here, said Kuon, the gap ranged from 5.4x to 87x worse for the FPGA, depending on process, voltage and temperature conditions--making it impossible to come up with a reliable measurement. The paper also said that area was on average 40 times worse, and delay two to five times worse, for the FPGA implementation.

Xilinx's Tuan noted that low standby power is crucial for mobile applications, and that ICs for such applications ideally dissipate less than 1 milliamp. But FPGAs may dissipate 10 to 500 mA, he noted. Pika claims to close that gap and bring FPGAs into an acceptable range for mobile, battery-powered products.